The Background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description which may not otherwise qualify as prior art at the time of filing, are neither expressly or impliedly admitted as prior art against the present disclosure.
Referring now to FIGS. 1, 2A and 2B, nonvolatile semiconductor memory 10 may include flash memory, static random access memory (SRAM), nitride read only memory (NROM), phase change memory, magnetic RAM, multi-state memory, etc. The nonvolatile semiconductor memory 10 may include one or more arrays 16. The array 16 may be arranged as B memory blocks 18-1, 18-2, . . . , and 18-B (collectively referred to as blocks 18).
In FIG. 2A, each block 18 includes P pages 20-1, 20-2, . . . , and 20-P (collectively referred to as pages 20). In FIG. 2B, each page 20 may include a plurality of memory cells that are associated with a data portion 24 and may include other memory cells that are associated with an overhead data portion 26 such as error checking and correcting (ECC) data or other (O) overhead data.
The nonvolatile semiconductor memory 10 typically communicates with a memory controller of a host device. Usually, the controller addresses the memory using a hardwired block size. Pages in the block may also have a hardwired page size. The number of memory cells in the data and overhead portions 24 and 26, respectively are also typically hardwired.
For example only, a typical NAND flash array may include 2048 blocks for a total of 2 Gigabytes (GB) of memory. Each block may comprise 128 kilobytes (kB) in 64 pages. Each page may include 2112 bytes. Of the 2112 bytes, 2048 bytes may be associated with the data portion and 64 bytes may be associated with the overhead portion. Each memory cell may store a bit. To erase data stored in the array, the memory controller typically requires either an entire block and/or an entire page to be erased.
In FIG. 2C, the memory block 18 includes predefined pages 50-1, 50-2, . . . , and 50-P (collectively referred to as pages 50). Each page 50 includes Y memory cells (memory cells 46-1, 46-2, . . . , and 46-Y) for the data portion and Z memory cells (memory cells 46-(Y+1), 46(Y+2), . . . , and 46(Y+Z)) for the overhead portion, where Y and Z are fixed values for a particular memory controller. During a first write operation for a first write data block, the memory controller writes data to pages 50-1 and 50-2 and part of page 50-3. During a second write operation for a second write data block, data is written to pages 50-4 and 50-5 and part of page 50-6. The remaining memory cells in pages 50-3 and 50-6 are unused, which is inefficient. Furthermore, the memory controller must be used with memory arrays having the same predefined configuration.